1. Field of the Invention
The present invention relates to a method of speech coding and decoding and a design of speech coder and decoder, more particularly to a method of speech coding and decoding and a design of speech coder and decoder that reduces the bit rate of the original speech from 64 Kbps to 1.6 Kbps.
2. Description of the Related Art
Basically, the main purpose of the digital speech coding is to digitize the speech, and appropriately compress and encode the digitized speech to lower the bit rate required for transmitting digital speech signals, reduce the bandwidth for signal transmission, and enhance the performance of the transmission circuit. Besides lowering the bit rate of the speech transmission, we also need to assure the compressed speech data received at the receiving end can be synthesized into the sound with reasonable speech quality. At present, various speech coding techniques invariably strive to lower the bit rate and improve the speech quality of the synthesized sound.
In the development of low bit rate encoder, the U.S. National Defense Department announced a new standard of 2.4 Kbps for the mixed excitation linear predictive (MELP) vocoder after the FS1016 CELP 4.8 Kbps and caused the trend of studying the decoder of 2.4 Kbps or lower. The inventor of the present invention studied the present 2.4 Kbps standard such as the LPC10 and the mixed excitation linear predictive vocoder, and then developed a 1.6 kbps speech compression method. The implementation of speech technology by hardware is the key to the commercialization of the speech product that makes the speech technology as part of our life. The present invention completes the design of the hardware structure of the 1.6 kbps vocoder by the ASIC architecture with an execution speed faster than the digital signal processor, and fits the system requiring fast computation speed such as the multiple-line coder, and its cost is also lower than the digital signal processor.